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june 2007 rev 8 1/39 1 M95512-W m95512-r 512 kbit serial spi bus eeprom with high speed clock features compatible with spi bus serial interface (positive clock spi modes) single supply voltage: ? 2.5 v to 5.5 v for M95512-W ? 1.8 v to 5.5 v for m95512-r high speed ? 5 mhz clock rate ? 5 ms write time status register hardware protection of the status register byte and page write (up to 128 bytes) self-timed programming cycle adjustable size read-only eeprom area enhanced esd protection more than 1 000 000 write cycles more than 40-year data retention packages ? ecopack? (rohs compliant) so8 (mn) 150 mils width tssop8 (dw) 169 mils width www.st.com
contents M95512-W, m95512-r 2/39 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 connecting to the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.3 power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M95512-W, m95512-r contents 3/39 6.3.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 ecc (error correction code) and write cycling . . . . . . . . . . . . . . . . . . 26 8 power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
list of tables M95512-W, m95512-r 4/39 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7. operating conditions (M95512-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 8. operating conditions (m95512-r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. dc characteristics (M95512-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. dc characteristics (m95128-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. ac characteristics (M95512-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. ac characteristics (m95512-r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . 35 table 17. ordering information scheme (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
M95512-W, m95512-r list of figures 5/39 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. so and tssop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. write enable (wren) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 8. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. read status register (rdsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 16. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17. output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . 34 figure 19. tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 35
description M95512-W, m95512-r 6/39 1 description these electrically erasable programmable memory (eeprom) devices are accessed by a high speed spi-compatible bus. the memory array is organized as 65536 x 8 bit. the device is accessed by a simple serial interface that is spi-compatible. the bus signals are c, d and q, as shown in ta b l e 1 and figure 1 . the device is selected when chip select (s ) is taken low. communications with the device can be interrupted using hold (hold ). in order to meet environmental requirements, st offers the M95512-W and m95512-r in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 1. logic diagram table 1. signal names signal name function direction c serial clock input d serial data input input q serial data output output s chip select input w write protect input hold hold input v cc supply voltage v ss ground ai01789c s v cc m95xxx hold v ss w q c d
M95512-W, m95512-r description 7/39 figure 2. so and tssop connections 1. see section 11: package mechanical for package dimensions, and how to identify pin-1. d v ss c hold q sv cc w ai01790d m95xxx 1 2 3 4 8 7 6 5
signal description M95512-W, m95512-r 8/39 2 signal description during all operations, v cc must be held stable and within the specified valid range: v cc (min) to v cc (max). all of the input and output signals must be held high or low (according to voltages of v ih , v oh , v il or v ol , as specified in ta b l e 1 1 and ta bl e 1 2 ). these signals are described next. 2.1 serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). 2.2 serial data input (d) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). 2.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) ch anges after the fa lling edge of serial clock (c). 2.4 chip select (s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the standby power mode. driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 2.5 hold (hold ) the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold conditio n, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select (s ) driven low.
M95512-W, m95512-r signal description 9/39 2.6 write protect (w ) the main purpose of this input signal is to freeze the size of the area of memory that is protected against write instructions (as specified by the values in the bp1 and bp0 bits of the status register). this pin must be driven either high or low, and must be stable during all write instructions. 2.7 v cc supply voltage v cc is the supply voltage. 2.8 v ss ground v ss is the reference for the v cc supply voltage.
connecting to the spi bus M95512-W, m95512-r 10/39 3 connecting to the spi bus these devices are fully compatible with the spi protocol. all instructions, addresses and input data bytes are shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select (s ) goes low. all output data bytes are shifted out of the device, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. figure 3. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. figure 3 shows an example of three memory devices connected to an mcu, on an spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, the other devices are high impedance. the pull-up resistor r (represented in figure 3 ) ensures that no device is selected if the bus master leaves the s line in the high impedance state. in applications where the bus master might enter a state where all inputs/outputs spi lines are in high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (c) must be connected to an external pull- down resistor so that, if all inputs/outputs become high impedance, the c line is pulled low (while the s line is pulled high). this ensures that s and c do not become high at the same time, and so, that the t shch requirement is met. ai12836b spi bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold rr r v cc v cc v cc v cc v ss v ss v ss v ss r
M95512-W, m95512-r connecting to the spi bus 11/39 the typical value of r is 100 k ? , assuming that the time constant r*c p (c p = parasitic capacitance of the bus line) is short enough, as the s and c lines must reach the correct state (s = high and c = low) while the spi bus is in high impedance. example: c p = 50 pf, that is r*c p = 5 s <=> the application must ensure that the bus master never leaves the spi bus in the high impedance state for a time period shorter than 5s. 3.1 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: cpol=0, cpha=0 cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from th e falling edge of serial clock (c). the difference between the two modes, as shown in figure 4 , is the clock polarity when the bus master is in stand-by mode and not transferring data: c remains at 0 for (cpol=0, cpha=0) c remains at 1 for (cpol=1, cpha=1) figure 4. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
operating features M95512-W, m95512-r 12/39 4 operating features 4.1 supply voltage (v cc ) 4.1.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta bl e 7 and ta b l e 8 .). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 4.1.2 power-up conditions when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s ) line is not allowed to float but should follow the v cc voltage, it is therefore recommended to connect the s line to v cc via a suitable pull-up resistor. in addition, the chip select (s ) input offers a built-in safety feature, as the s input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on chip select (s ). this ensures th at chip select (s ) must have been high, prior to going low to start the first operation. the v cc rise time must not vary faster than 1 v/s. 4.1.3 power-up and device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any instruction until v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in ta bl e 7 and ta b l e 8 ). when v cc has passed the por threshold, the device is reset and in the following state: standby power mode deselected (at next power-up, a falling edge is required on chip select (s ) before any instructions can be started) not in the hold condition status register state: the write enable latch (wel) is reset to 0 write in progress (wip) is reset to 0. the srwd, bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits)
M95512-W, m95512-r operating features 13/39 4.1.4 power-down at power-down (continuous decrease in v cc ), as soon as v cc drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any inst ruction sent to it. during power-down, the device must be deselected and in standby power mode (that is there should be no internal write cycle in progress). chip select (s ) should be allowed to follow the voltage applied on v cc . 4.2 active power and standby power modes when chip select (s ) is low, the device is selected, and in the active power mode. the device consumes i cc , as specified in ta b l e 1 2 . when chip select (s ) is high, the device is deselected. if a write cycle is not currently in progress, the device then goes in to the standby power mode, and the device consumption drops to i cc1 . 4.3 hold condition the hold (hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. during the hold conditio n, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device must be selected, with chip select (s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. the hold condition starts when the hold (hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in figure 5 ). the hold condition ends when the hold (hold ) signal is driven high at the same time as serial clock (c) already being low. figure 5 also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low.
operating features M95512-W, m95512-r 14/39 figure 5. hold condition activation 4.4 status register figure 6 shows the position of the status register in the control logic of the device. the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. see section 6.3: read stat us register (rdsr) for a detailed description of the status register bits 4.5 data protection and protocol control non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. consequently, the device features the following data protection mechanisms: write and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ?power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? write (write) instruction completion the block protect (bp1, bp0) bits in the status register allow part of the memory to be configured as read-only. this is the software protected mode (spm). the write protect (w ) signal allows the block protect (bp1, bp0) bits to be protected. this is the hardware protected mode (hpm). for any instruction to be accepted, and executed, chip select (s ) must be driven high after the rising edge of serial clock (c) for the last bit of the instruction, and before the next rising edge of serial clock (c). two points need to be noted in the previous sentence: the ?last bit of the instruction? can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for read status register (rdsr) and read (read) instructions). the ?next rising edge of serial clock (c)? might (or might not) be the next bus transaction for some other device on the spi bus. ai02029d hold c hold condition hold condition
M95512-W, m95512-r operating features 15/39 table 2. write-protected block size status register bits protected block array addresses protected bp1 bp0 0 0 none none 0 1 upper quarter c000h - ffffh 1 0 upper half 8000h - ffffh 1 1 whole memory 0000h - ffffh
memory organization M95512-W, m95512-r 16/39 5 memory organization the memory is organized as shown in figure 6 . figure 6. block diagram ai01272c hold s w control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder c d q size of the read only eeprom area status register
M95512-W, m95512-r instructions 17/39 6 instructions each instruction starts with a sing le-byte code, as summarized in ta bl e 3 . if an invalid instruction is sent (one not contained in ta b l e 3 ), the device automatically deselects itself. 6.1 write enable (wren) the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 7 , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s ) being driven high. figure 7. write enable (wren) sequence table 3. instruction set instruction description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 c d ai02281e s q 2 1 34567 high impedance 0 instruction
instructions M95512-W, m95512-r 18/39 6.2 write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 8 , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be dese lected, by chip select (s ) being driven high. the write enable latch (wel) bit, in fact, becomes reset by any of the following events: power-up wrdi instruction execution wrsr instruction completion write instruction completion. figure 8. write disable (wrdi) sequence c d ai03750d s q 2 1 34567 high impedance 0 instruction
M95512-W, m95512-r instructions 19/39 6.3 read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a write or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 9 . the status and control bits of the status register are as follows: 6.3.1 wip bit the write in progress (wip) bit indicates whet her the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.3.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write or write status register instruction is accepted. 6.3.3 bp1, bp0 bits the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in ta bl e 4 ) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. 6.3.4 srwd bit the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. table 4. status register format b7 b0 srwd 0 0 0 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
instructions M95512-W, m95512-r 20/39 figure 9. read status register (rdsr) sequence c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
M95512-W, m95512-r instructions 21/39 6.4 write status register (wrsr) the write status register (wrsr) instruction a llows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruct ion is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 10 . the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 are always read as 0. chip select (s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. figure 10. write status register (wrsr) sequence c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
instructions M95512-W, m95512-r 22/39 the write status register (wrsr) instruction allows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read- only, as defined in ta b l e 4 . the write status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hardware protected mode (hpm) is entered. the contents of the status register write disable (srwd) and block protect (bp1, bp0) bits are frozen at their current values from just before the start of the execution of write status register (wrsr) instruction. the new, updated, values take effect at the moment of completion of the execution of write status register (wrsr) instruction. the protection features of the device are summarized in ta bl e 2 . when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) in struction, regardless of the whether write protect (w ) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w ): if write protect (w ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. if write protect (w ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp1, bp0) bits of the status register, are also hardware protected against data modification. table 5. protection modes w signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the block protect ( bp1, bp0) bits of the status register, as shown in table 5 . unprotected area (1) 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the bp1 and bp0 bits can be changed write protected ready to accept write instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the bp1 and bp0 bits cannot be changed write protected ready to accept write instructions
M95512-W, m95512-r instructions 23/39 regardless of the order of the two events, the hardware protected mode (hpm) can be entered: by setting the status register write disabl e (srwd) bit after driving write protect (w ) low or by driving write protect (w ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w ) high. if write protect (w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp1, bp0) bits of the status register, can be used. 6.5 read from memory array (read) as shown in figure 11 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). the address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select (s ) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. when the highest address is reached, the addr ess counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruction. the read cycle is terminated by driving chip select (s ) high. the rising edge of the chip select (s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not executed, if a write cycle is currently in progress. figure 11. read from memory array (read) sequence c d ai01793d s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 76543 1 7 0 high impedance data out 1 instruction 16-bit address 0 msb msb 2 31 data out 2
instructions M95512-W, m95512-r 24/39 6.6 write to memory array (write) as shown in figure 12 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select (s ) high at a byte boundary of the input data. in the case of figure 12 , this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is be ing used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in ta bl e 1 4 ), at the end of which the write in progress (wip) bit is reset to 0. if, though, chip select (s ) continues to be driven low, as shown in figure 13 , the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. the self- timed write cycle starts, and continues, for a period t wc (as specified in ta b l e 1 4 ), at the end of which the write in progress (wip) bit is reset to 0. each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. if the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (the page size of these devices is 128 bytes). the instruction is not accepted, and is not executed, under the following conditions: if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) if a write cycle is already in progress if the device has not been deselected, by chip select (s ) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. figure 12. byte write (write) sequence c d ai01795d s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 high impedance instruction 16-bit address 0 765432 0 1 data byte 31
M95512-W, m95512-r instructions 25/39 figure 13. page write (write) sequence c d ai01796d s 34 33 35 36 37 38 39 40 41 42 44 45 46 47 32 c d s 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 instruction 16-bit address 0 765432 0 1 data byte 1 31 43 765432 0 1 data byte 2 765432 0 1 data byte 3 65432 0 1 data byte n
ecc (error correction code) and write cycling M95512-W, m95512-r 26/39 7 ecc (error correction code) and write cycling the M95512-W and m95512-r devices offer an ecc (error correction code) logic which compares each 4-byte word with its associated 6 eeprom bits of ecc. as a result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation, the ecc detects it and replaces it by the correct value. the read relia bility is therefor e much improved by the use of this feature. note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ecc bits), that is, the addressed byte is cycled together with the other three bytes making up the word. it is therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of write cycles. the M95512-W and m95512-r devi ces are qualified at 1 million (1 000 000) write cycles, using a cycling routine that writes to th e device by multiples of 4-byte packets. 8 power-up and delivery state 8.1 power-up state after power-up, the device is in the following state: standby power mode deselected (after power-up, a falling edge is required on chip select (s ) before any instructions can be started). not in the hold condition write enable latch (wel) is reset to 0 write in progress (wip) is reset to 0 the srwd, bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). 8.2 initial delivery state the device is delivered with the memory array set at all 1s (ffh). the status register write disable (srwd) and block protect (bp1 and bp0) bits are initialized to 0.
M95512-W, m95512-r maximum rating 27/39 9 maximum rating stressing the device outside the ratings listed in ta bl e 6 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020c (for smal l body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu c v o output voltage ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (2) 2. aec-q100-002 (compliant wi th jedec std jesd22-a114a, c1=100pf, r1=1500 ? , r2=500 ? ) ?4000 4000 v
dc and ac parameters M95512-W, m95512-r 28/39 10 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 14. ac measurement i/o waveform table 7. operating conditions (M95512-W) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c table 8. operating conditions (m95512-r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 9. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v table 10. capacitance (1) 1. not 100% tested. symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0 v 8 pf c in input capacitance (d) v in = 0 v 8 pf input capacitance (other pins) v in = 0 v 6 pf ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
M95512-W, m95512-r dc and ac parameters 29/39 table 11. dc characteristics (M95512-W, device grade 6) symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current (read) c = 0.1v cc /0.9v cc at 5 mhz, v cc = 2.5 v, q = open 3ma c = 0.1v cc /0.9v cc at 5 mhz, v cc = 5 v, q = open 5ma i cc0 (1) 1. characterized value, not tested in production. supply current (write) during t w , s = v cc , 2.5 v < v cc < 5.5 v 5ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc , 2.5 v < v cc < 5.5 v 5a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage v cc = 2.5 v and i ol = 1.5 ma or v cc = 5 v and i ol = 2 ma 0.4 v v oh output high voltage v cc = 2.5 v and i oh = ?0.4 ma or v cc = 5 v and i oh = ?2 ma 0.8 v cc v table 12. dc characteristics (m95128-r) symbol parameter test condition min max unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current (read) c = 0.1v cc /0.9v cc at 2 mhz, v cc = 1.8 v, q = open 1ma i cc0 (1) 1. characterized value, not tested in production. supply current (write) during t w , s = v cc , 1.8 v < v cc < 2.5 v 3ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc , 1.8 v < v cc < 2.5 v 3a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v 0.3 v v oh output high voltage i oh = ?0.1 ma, v cc = 1.8 v 0.8 v cc v
dc and ac parameters M95512-W, m95512-r 30/39 table 13. ac characteristics (M95512-W, device grade 6) test conditions specified in table 9 and table 7 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 ns t shch t css2 s not active setup time 90 ns t shsl t cs s deselect time 100 ns t chsh t csh s active hold time 90 ns t chsl s not active hold time 90 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 90 ns t cl (1) t cll clock low time 90 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 20 ns t chdx t dh data in hold time 30 ns t hhch clock low hold time after hold not active 70 ns t hlch clock low hold time after hold active 40 ns t clhl clock low set-up time before hold active 0 ns t clhh clock low set-up time before hold not active 0 ns t shqz (2) t dis output disable time 100 ns t clqv t v clock low to output valid 60 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 50 ns t qhql (2) t fo output fall time 50 ns t hhqv t lz hold high to output valid 50 ns t hlqz (2) t hz hold low to output high-z 100 ns t w t wc write time 5 ms
M95512-W, m95512-r dc and ac parameters 31/39 table 14. ac characteristics (m95512-r) test conditions specified in table 9 and table 8 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 2 mhz t slch t css1 s active setup time 200 ns t shch t css2 s not active setup time 200 ns t shsl t cs s deselect time 200 ns t chsh t csh s active hold time 200 ns t chsl s not active hold time 200 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 200 ns t cl (1) t cll clock low time 200 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 40 ns t chdx t dh data in hold time 50 ns t hhch clock low hold time after hold not active 140 ns t hlch clock low hold time after hold active 90 ns t clhl clock low set-up time before hold active 0 ns t clhh clock low set-up time before hold not active 0ns t shqz (2) t dis output disable time 250 ns t clqv t v clock low to output valid 150 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 100 ns t qhql (2) t fo output fall time 100 ns t hhqv t lz hold high to output valid 100 ns t hlqz (2) t hz hold low to output high-z 250 ns t w t wc write time 5 ms
dc and ac parameters M95512-W, m95512-r 32/39 figure 15. serial input timing figure 16. hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c q ai01448b s d hold tclhl thlch thhch tclhh thhqv thlqz
M95512-W, m95512-r dc and ac parameters 33/39 figure 17. output timing c q ai01449e s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
package mechanical M95512-W, m95512-r 34/39 11 package mechanical figure 18. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 15. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k0808 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
M95512-W, m95512-r package mechanical 35/39 figure 19. tssop8 ? 8 lead thin shrink small outline, package outline 1. drawing is not to scale. table 16. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 n8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
part numbering M95512-W, m95512-r 36/39 12 part numbering 1. ordering information related to the M95512-W and m95512-r identified with the process letter "a". for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 17. ordering information scheme (1) example: m95512 ? w mn 6 t p device type m95 = spi serial access eeprom device function 512 = 512 kbit (65536 8) operating voltage w = v cc = 2.5 v to 5.5 v r = v cc = 1.8 v to 5.5 v package mn = so8 (150 mil width) dw = tssop8 (169 mil width) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow option blank = standard packing t = tape and reel packing plating technology p or g = ecopack? (rohs compliant)
M95512-W, m95512-r revision history 37/39 13 revision history table 18. document revision history date revision changes jan-1999 1.0 document written 13-feb-2002 2.0 document reformatted using the new template voltage range -s added, and -r removed instruction sequence illustrations updated announcement made of planned upgrade to 10 mhz clock for the 5v, ?40 to 85c, range 05-dec- 2003 3.0 table of contents, and pb-free options added. v il (min) improved to -0.45v. voltage range -r added, and -s removed 02-apr-2004 4.0 old versions of document complete ly replaced by one rewritten from m95256 03-jan-2005 5.0 ac and dc characteristics tables updated with the performance data of the new device identified with the process letter ?a?. table 1., product list added. aec-q100-002 compliance. device grade information clarified. t hhqx , t chhl and t chhh corrected to t hhqv , t clhl and t clhh , respectively. m95512 part number with 4.5v to 5.5v operating voltage range removed (related tables removed). document status changed to preliminary data. 30-jun-2005 6.0 updated figure 3: bus master and memory devices on the spi bus and figure 16: hold timing . power on reset information clarified. protected array addresses modified in table 2: write-protected block size . ambient operating temperature value added in table 6: absolute maximum ratings . supply current (i cc ) value modified for 10 mhz in table 11: dc characteristics (M95512-W, device grade 6) . all values modified in table 14: ac characteristics (m95512-r) . document status changed to datasheet. 06-feb-2007 7 document reformatted. packages are ecopack? compliant. 10 mhz frequency removed. v cc supply voltage and v ss ground descriptions added. figure 3: bus master and memory devices on the spi bus modified and explanatory paragraph added. power-up and power on reset paragraphs replaced by section 4.1: supply voltage (v cc ) . section 7: ecc (error correction code) and write cycling added. t a max modified in table 7: operating conditions (M95512-W) . note modified below table 10: capacitance . c l modified in and table 9: ac measurement conditions . v il max and i cc0 test conditions modified in table 12: dc characteristics (m95128-r) . i cc modified in table 11: dc characteristics (M95512-W, device grade 6) , i cc0 added to ta b l e 1 1 and table 12: dc characteristics (m95128-r) modified. table 14: ac characteristics (m95512-r) modified. t shqz end timing line moved back in figure 17: output timing . so8n package specifications updated (see figure 18 and ta bl e 1 5 ). blank removed below plating technology in table 17: ordering information scheme (1) .
revision history M95512-W, m95512-r 38/39 05-jun-2007 8 the device endurance is specified at more than 1 000 000 (1 million) cycles (corrected on page 1 ). table 18. document revision history (continued) date revision changes
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